Plated shut through hole vias use a full copper plating process to completely fill vias, eliminating voids, air pockets, and fluid entrapment that can lead to failures under thermal stress. This approach provides a solid copper core that improves thermal conductivity, signal performance, and surface planarity compared to traditional filled via methods. While moreit is more complex and costly to manufacture, the performance advantages make it ideal for demanding PCB applications.
Plated shut through hole vias are an advanced PCB fabrication method designed to fully fill through holes with copper using a controlled plating process. Unlike traditional via fill techniques that rely on conductive or non-conductive materials, this approach produces a solid copper structure inside the via barrel.
Many experienced PCB designers are familiar with plated shut microvias, but fully plated shut through hole vias require a more specialized process that not all fabricators can support. A refined plating methodology enables complete filling of through holes up to 12 mils in diameter while preventing voids, air pockets, and fluid entrapment. These defects are common risks in conventional processes and often only become apparent during thermal stress conditions.
Through vias are illustrated in blue and copper plated shut vias are shown in yellow.
Actual circuit board with copper plated shut vias
Traditional PCB plating methods are not suitable for plated shut through hole vias. Standard processes tend to introduce hidden defects due to uneven copper deposition rates within the via.
Cross Section of 12 Mil Hole on 62 Mil Thick Multilayer PCB
To address these limitations, a controlled plating process is used to ensure uniform copper fill throughout the entire via. Cross-section validation confirms complete filling with no voids or outgassing.
A single-step DC plating approach is often considered ideal for copper filling because it simplifies the plating line. However, this method can require extended processing times, with plating durations exceeding 15 to 18 hours for thicker substrates.
Copper plated shut vias provide measurable improvements in thermal, electrical, and assembly performance when compared to conductive and non-conductive filled vias.
Traditional fill materials can shrink during curing, resulting in a slight surface depression. Fully plated copper vias eliminate this issue by slightly overfilling prior to planarization, resulting in a flat surface.
This large differential makes copper-filled vias the preferred choice for applications requiring efficient heat transfer.
Conductive fill materials can introduce resistance at higher frequencies, reducing signal integrity. A solid copper-filled via provides a more effective electrical path with reduced losses.
The primary tradeoff associated with plated shut through hole vias is increased manufacturing complexity.
Despite these factors, the performance gains in thermal management, signal integrity, and reliability often outweigh the added cost in high-performance applications.
The solid copper core created by the plating process delivers a flat, planar surface after finishing. This uniform surface prevents solder from flowing into the via during assembly, which helps maintain consistent solder joints and improves overall assembly reliability.
| Parameter | Value | Units |
|---|---|---|
| Maximum via diameter | Up to 12 | mils |
| DC plating time | >15 to 18 | hours |
| Thermal conductivity (non-conductive fill) | 0.25 | W/mK |
| Thermal conductivity (conductive paste) | 3.5–15 | W/mK |
| Thermal conductivity (copper) | >250 | W/mK |
Plated shut vias are used when thermal performance, structural integrity, and signal quality are critical. They are particularly beneficial where traditional filled vias may fail under thermal stress.
Through hole vias can become points of failure if voids or trapped materials are present. A fully plated copper via eliminates these risks by creating a solid, continuous structure.
Copper provides significantly higher thermal conductivity and improved electrical performance compared to alternative fill materials. However, it requires a more controlled and time-intensive plating process.
Standard plating processes are not suitable because copper deposits unevenly, which can lead to premature surface closure and trapped chemistry inside the via. A controlled plating process is required to ensure uniform fill and eliminate voids.
The controlled copper plating process requires extended plating durations to achieve a complete, void-free fill. In many cases, plating times exceed 15 to 18 hours, contributing to longer overall processing time.
Unlock superior thermal performance and signal integrity with our copper plated shut vias. Experience the difference today.
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