PCB Surface Finish Options

Not all circuit board surface finishes are alike. In order for a PCB engineer to specify which surface finish is right for the application, you need to look deeply into what the PCB will be exposed to during its lifetime.

Something as small as the amount of hand soldering or potential field repairs will play a big role in your choice of the best surface finish for your printed circuit board. For additional information, we also have a technical article on the advantages and disadvantages of surface finishes that will help with the selection for your PCB design.

Below are some of the detailed parameters of the most common surface finishes used in the PCB industry.

  Tin Lead HASL ENIG Ni & Hard Au OSP Immersion Silver Immersion Tin
Lead Free HASL ENEPIG Ni & Soft Au ImAg
Design Attribute
Hole Compensation Require 0.002 - 0.003 in. STD 0.001 in. / Design Dependent STD STD STD
Minimum Cleared Hole Size max 6:1 aspect ratio * No Limitation No Limitation No Limitation No Limitation No Limitation
Via Caps (post surface finish) UV / Thermal UV / Thermal UV / Thermal UV only UV UV only
Electrical Contact Use Fair Good for Low Wear Applications Hard Au: Excellent

Soft Au: Not Recommended
Not Recommended Good for Low Wear Applications Good for Low Wear Applications

Pre sm = design dependent
Yes if Tie bar Only Only Only
Exposed Copper None None Trace Edges (if not tie bar) Un-assembled features after assembly None None
Manufacturing Process
Process Automation Conveyorized or Vertical Vertical only Vertical Conveyorized Conveyorized or Vertical Conveyorized or Vertical
Environmental & Process Hazards High (Lead & Thermal) Medium Medium Low Low High (Thiourea)
Quality Concerns QFP Shorting / uBGA / Flatness Skip/Extraneous Plate Resist Lifting

Plating Distribution
Handling Handling SM Attack / Handling
Gold Contacts Tie bar ok

Other: Design dependent
Low volume / Tie Bar Thin Hard Au solderable

Thick Hard Au for contact

Thick Soft Au for Au wire bonding
No Limitation Design Dependent
(masking consideration)
Tie bar ok

Other: Design Dependent
Finished PCB Rework Ability Design Dependent ENIG: Limited to Ni & Au brush

ENEPIG: Unknown
Limited to Nickel & Gold brush Easy Limited Medium
Equipment Maintenance Intensive Typical Vertical Process Typical Vertical Process Low Low Low
Thickness Measurement XRF on Product XRF on Product XRF on Product Spectrophotometer on Test Coupon XRF on Product XRF on Product
Manufacturability Tin-Lead: 2

Lead-Free: 3

3 1 1 3
Assembly Considerations
Thickness Deposit 50 to 1500 uin

IMC layer and planarity consideration
ENIG:2 to 6 uin Au / 150 to 250 uin Ni

ENEPIG wide range
(being defined by IPC committee)
Hard Au for solderability 5 to 15 uin

Hard Au for contacts 30 to 50 uin

Soft Au for wire bonding 40+ uinover a minimum of 150 uin of Ni
6 to 24 micro-inch chemistry dependent 6 to 18 uin 30 to 40 uinch minimum
Features Spacing Less than 20 mils QFP = Limited No limitation for SMOBC

Preferably > 4 mils prior to SM
Line width & space and aspect ratio limitation No Limitation No Limitation No Limitation
Solder Paste Misprint Normal Wipe Down Normal Wipe Down Normal Wipe Down Reduces Hold Times between Reflows Supplier guidelines (cleaner restrictions) Normal Wipe Down
Lead Free Assembly Compatible Tin-lead: No

Lead Free: Yes
Yes Yes Yes

The newer generations
Yes Limited to the number of reflow cycle
Other Considerations
Intermetallic Layer Tin Copper ENIG: Tin-Nickel

ENEPIG: Tin- Palladium
Tin-Nickel Tin Copper Tin Copper Tin Copper
Solder Joint Strength Good for Tin-lead

Limited data for lead free
ENIG: Good (Large BGA Issues) Good Excellent Excellent Good
Surface Finish Durability Tin-lead: Good

Lead Free: Unknown
Very Good Very Good Handling considerations Handling and storage conditions Good
Various Thermal shock
(preheat and solder bath)

Lead Free: pre baking
ENIG: Ni layer for RF applications

ENEPIG: Good for Au wire bonding
Nickel Layer for RF application Holding time between assembly cycles Storage, exposure to sulfur and halides >Limited reflow cycle capability

>Good for back plane applications

>Intermetallic layer

* Equipment dependent
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Our History

As the oldest production Printed Circuit Board Company in North America, perhaps in the world, the 60-year plus story of Epec is connected to the development of the PCB and the electronics industry.

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  • Epec Founded in 1952
  • IPC Founded in 1957
  • Epec Builds PCB for Apollo 11